A programmable logic device (PLD) requires configuration by the user before normal operation. Various programming tools exist that enable a user to shift in configuration data into the PLD to effect a desired logical function. There are corresponding types of elements or components that are configured by the resulting stored configuration data within the PLD. The primary component being configured may be referred to as the programmable fabric—in the case of a field programmable gate array (FPGA), the programmable fabric includes a plurality of lookup-table-based logic blocks as well as an associated routing structure. The configuration data for the programmable fabric is typically stored in a volatile FPGA memory (SRAM) and is shifted into the device through a dedicated data shift register (DSR). In contrast, critical control information such as clock trim levels, encryption keys, and passwords are shifted into the device through a separate dedicated data shift register.
The critical control information is stored in a non-volatile memory such as flash or an embedded non-volatile memory such as a one-time programmable (OTP) memory. But the resulting stored information is not accessed by the configured PLD directly from the non-volatile memory. Instead, the control information is first copied into corresponding shadow registers. This is done because the shadow registers are faster to read from as opposed to reading from the non-volatile memory. Thus, the configured PLD accesses the critical information from the shadow registers (as opposed to reading the non-volatile memory) during normal operation. In addition, the contents of the non-volatile memory are thus not disturbed during normal operation. But the shadow registers are not directly programmed during configuration of a conventional PLD.
Instead, the desired control information is shifted through the dedicated data shift register into the non-volatile memory. The programming tool may then read back from the non-volatile memory to ensure that the desired information was written correctly. But there is no ability to debug the device prior to writing to the non-volatile memory. This is problematic, particularly when the non-volatile memory is a one-time programmable (OTP) memory such that the data is permanently and irreversibly written.
Accordingly, there is a need in the art for PLDs that enable testing normal operation with critical control information before the critical control information is written to non-volatile memories within the PLDs.